1. Field
Apparatuses and methods consistent with exemplary embodiments relate to canceling noise in an image sensor, and more particularly to canceling noise by aggregating pseudo correlated double sampling (CDS) output signals with full integration.
2. Description of the Related Art
A related art complementary metal-oxide-semiconductor (CMOS) imaging sensor typically includes an array of image sensing pixels. FIG. 1 illustrates a circuit diagram of a related art image sensing pixel 100, which is referred to as a 4T pixel because the pixel 100 includes four transistors. As shown in FIG. 1, the 4T pixel 100 also includes a photodetector PD, which generates a current in response to detecting incident light. The generated current is accumulated (or integrated) to generate a voltage, which is read out of the 4T pixel 100 as an output signal. To reset the pixel, a reset transistor RST is turned on. Furthermore, to start a new integration period, the reset transistor RST is turned off, thereby allowing the generated current to integrate. The integration period of a pixel corresponds to a period between resets of the pixel.
A major source of noise in the image sensing pixels is the reset transistor RST, which can exhibit reset noise such as flicker noise, thermal noise (i.e., kTC noise), and other types of noise. One related art technique to reduce reset noise in the 4T pixel is correlated double sampling (CDS). Generally, CDS is a method to measure an electrical value that allows removal of an undesired offset based on two output measurements, i.e., an output measurement in a known condition and an output measurement in an unknown condition. When used in a CMOS imaging sensor, CDS is a noise-reduction technique based on a difference between a reference voltage (i.e., reset voltage after the pixel is reset) and a signal voltage (i.e., the pixel's voltage at the end of integration) at the end of each integration period.
FIG. 2 illustrates an example timing diagram of the related art on-chip CDS. As an example, for on-chip CDS, the related art 4T pixel 100 has a general operation order including sample reset voltage, charge transfer, and sample signal voltage for each integration period. The sample reset and the signal sample have a correlated kTC component, while flicker noise may generally be high at low frequency only.
In detail, as shown in FIG. 2, the reset voltage Vrst corresponds to Vrst=Vr+Nktc+Nf(r), where Vr is the ideal reset voltage, Nktc is the correlated thermal noise component, and Nf(r) is the flicker noise component at the reset. Furthermore, the signal voltage Vsig corresponds to Vsig=Vr+Nktc+Nf(s)−Vlight, where Nf(s) is the flicker noise component at the signal sample and Vlight is the illuminance voltage, i.e., integrated voltage value corresponding to illuminance.
The correlated thermal noise component Nktc is canceled out by the difference between the signal voltage and the reset voltage: Vrst−Vsig=Vlight+Nf(r)−Nf(s). Moreover, when the time difference between the sample reset and the signal sample is short such that Nf(r)=Nf(s), the flicker noise components Nf(r) and Nf(s) can also be canceled by the difference between the signal voltage and the reset voltage, such that only the illuminance voltage Vlight is left.
For CMOS imaging sensors including low transistor count pixels, such as sensors with 3T or 5T pixels, or binary sensors with 1T or 2T pixels, the on-chip CDS is not applicable. FIG. 3 illustrates a circuit diagram of a related art 3T pixel 300. In this case, a related art pseudo-CDS technique or a related art off-chip CDS technique can be used. FIG. 4 illustrates an example timing diagram of the related art pseudo-CDS and the related art off-chip CDS.
In the related art pseudo-CDS, the signal voltage is sampled and then the subsequent reset voltage for the next integration period is sampled and a difference therebetween is read out. However, this approach will not cancel or reduce the kTC noise. In detail, as shown in FIG. 4, the reset voltage Vrst(1) at pseudo-CDS readout interval (1) corresponds to Vrst(1)=Vr+Nktc(1)+Nf(r1), where Vr is the ideal reset voltage, Nktc(1) is the thermal noise component at the reset of a second integration period (1), and Nf(r1) is the flicker noise component at the reset in the readout interval (1). Furthermore, the signal voltage Vsig(1) at the particular readout interval (1) corresponds to Vsig(1)=Vr+Nktc(0)+Nf(s1)−Vlight, where Nktc(0) is the thermal noise component at the signal of a first integration period (0) preceding the abovementioned second integration period, Nf(s1) is the flicker noise component at the signal in the readout interval (1), and Vlight is the illuminance voltage.
Thus, using pseudo-CDS, the difference between the signal voltage and the reset voltage can cancel the flicker noise Nf, since Nf(1)=Nf(r1)=Nf(s1), but cannot cancel the thermal noise component since Nktc(0) and Nktc(1) of the different integration periods are not correlated: Vrst(1)−Vsig(1)=Vlight+Nktc(1)−Nktc(0).
Meanwhile, the related art off-chip CDS involves saving a reset frame then a signal frame and subtracting the signal frame from the reset frame: Vrst(0)−Vsig(1)=Vlight+Nf(0)−Nf(1). In this approach, although the kTC noise can be canceled since the reset and signal are correlated, the flicker noise cannot be canceled because its level changes without correlation after integration. In addition, the off-chip CDS utilizes additional components (e.g., memory).